The present invention relates generally to semiconductor devices and more particularly to methods for fabricating transistors in a semiconductor device.
MOSFETs and other types of transistors are found in many modern semiconductor products where switching and/or amplification functions are needed. Many manufacturing processes and techniques have been developed for forming MOSFET devices in semiconductor substrate materials such as silicon and the like. In recent years, the size of transistors and other components have steadily decreased to submicron levels in order to facilitate higher device densities in semiconductor products. At the same time, many applications of such devices have created a need to operate the semiconductor devices at lower power and voltage levels. For instance, many wireless communications devices and portable computer systems are operated from batteries. Thus, where previous MOSFET devices were designed to operate at voltages of 5 or more volts, newer applications may require such devices to operate from DC supplies of around 3 volts or less. Accordingly, efforts continue to be made to design semiconductor devices, such as MOSFET transistors, which consume less power and operate at lower voltages.
As the power supply voltages at which MOSFET transistors operate have been steadily decreased, the transistor operating specifications have changed as well. Thus, for example, decreasing the voltage at which a MOSFET transistor is to operate allows thinner gate oxide to be used in forming the MOSFET gate structure. In addition, the doping concentrations in the source/drain regions of the MOSFET have typically been increased to facilitate low power/low voltage operation. However, many applications continue to require transistors which operate at higher voltage levels, in addition to those devices designed to operate at low voltages. For example, semiconductor products are often required to interface with equipment such as printers, control systems, or the like, which generate signals at relatively high voltage levels, such as 12 volts DC.
In these situations, it is desirable to fabricate transistors designed for low power consumption and low voltage operation, as well as those designed for higher voltages, in a single semiconductor device or product. Accordingly, some MOSFETs in these products will have thin gate oxides (e.g., for the low voltage transistors), whereas others will have thicker gate oxides. Fabrication of such products is thus sometimes referred to as a split gate oxide process. In addition to formation of two or more gate oxide structures of different thicknesses, other processing considerations need to be accounted for in designing and producing such products. For instance, source/drain doping concentrations may need to be higher in the low voltage MOSFETs than in higher voltage transistors in order to achieve the desired operating parameters for both type devices. In this regard, it is noted that the formation of low voltage MOSFET device source/drain regions already includes two separate processing steps (e.g., implantations) in situations where both P type and N type MOSFET transistors are needed. Although separate source/drain formation steps (e.g., such as separate implantation processes) may be used to provide appropriate doping concentrations for the low voltage and higher voltage MOSFET source/drain regions, the extra processing steps increase the product cost, and may render such an approach commercially uncompetitive.
Thus, it is desirable, where possible, to reduce the number and complexity of extra processing steps required to form both low voltage and higher voltage MOSFET devices in a single semiconductor product. One possibility is to apply the same source/drain implantation process to both the high voltage and the low voltage MOSFET devices, for each type (e.g., N and P). For instance, a lightly doped drain (LDD) implantation process optimized to implant phosphorus or arsenic in source/drain regions of low voltage (e.g., 3 volt) NMOS devices can also be used to implant higher voltage (e.g., 7 volt) NMOS source/drain regions, thereby reducing the number of processing steps. Similarly, an LDD implantation of boron in the source/drain regions of low voltage (e.g., 3 volt) PMOS devices can also be used to implant higher voltage (e.g., 7 volt) PMOS transistor source/drain regions.
However, it has been found that employing such implantation processes for both low and high voltage MOSFET devices results in high substrate currents and channel hot carrier degradation (CHC) in the high voltage devices where the implant is optimized for the low voltage MOSFETs, which in turn may lead to performance degradation and/or device damage. For instance, where source/drain regions of the high voltage NMOS devices are implanted using a high dosage implant optimized for the low voltage MOSFETS, high substrate current may cause injection of hot electron carriers into the gate oxide above the silicon substrate. In this regard, it has been found that the higher dopant concentration, combined with the higher operating voltages, cause higher than desired electric fields, which in turn cause hot carrier generation. The injected hot carriers, in turn, often lead to undesired degradation of MOSFET device operating parameters, such as a shift in threshold voltage, changed transconductance, changed drive current/drain current exchange, and device instability. In particular, the LDD dose used to form the low voltage MOSFET device source/drain regions (e.g., for the devices having the thinner gate oxide) is typically too high for the high voltage devices (e.g., having thicker gate oxide) to ensure low substrate current and acceptable hot carrier degradation. Thus, there is a need for improved manufacturing methodologies for fabricating both low and high voltage MOSFET devices in a semiconductor product, by which substrate current and CHC degradation can be controlled, without adversely increasing the number of processing steps.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention relates to semiconductor device fabrication, wherein source/drain regions in one transistor are implanted using a threshold voltage (VT) adjust implantation, which is concurrently also being used to adjust the threshold voltage of another transistor. Using this technique, the source/drain regions of high voltage MOSFET devices can be implanted while adjusting the threshold voltage of lower voltage MOSFETS. Thus, the somewhat lower dosage implant can simultaneously or contemporaneously be used to implant the channel (e.g., or indeed the entire active area) associated with a low voltage device, along with the source/drain regions of a higher voltage device, for example, using appropriate VT adjust implantation masking. The high voltage device source/drain regions can then be masked from subsequent LDD implantation of the low voltage device source/drain regions. As a result, the appropriate dopant concentrations are achieved in both the high and low voltages devices, without adding extra processing steps, such as separate LDD implants for each type device. Thus, the invention can be advantageously employed in split gate oxide device processing to control CHC degradation without adversely impacting product cost.
One aspect of the invention relates to a method of fabricating MOSFET transistors in a semiconductor device, which involves implanting a first transistor region associated with a first transistor device in the semiconductor device using a first implantation process to adjust a threshold voltage associated with the first transistor device, and implanting a portion of a second transistor region associated with a second transistor to form a source/drain region associated with the second transistor using the first implantation process. The first implantation process, for example, may be a threshold voltage (VT) adjust implant optimized for adjusting threshold voltages associated with low voltage MOSFET transistors in the device. A first gate oxide structure may be formed overlying a channel region in the first transistor region, and a second gate oxide structure is formed overlying a channel region in the second transistor region, where the second gate oxide structure is thicker than the first gate oxide structure. Source/drain regions for the first transistor can then be formed by implanting a portion of the first transistor region using a second implantation process, such as an LDD implant optimized for low voltage device source/drain formation.
In one implementation, for example, the first implant may employ boron to adjust the threshold voltages of low voltage (e.g., 3 volt) NMOS transistors, as well as to form the source/drain regions of high voltage (e.g., 7 volt) PMOS devices. Where both NMOS and PMOS devices (e.g., high and low voltage) are needed in a particular semiconductor product, similar processing using arsenic or phosphorus may be employed for VT adjust of low voltage PMOS devices and source/drain formation for high voltage NMOS devices. In such a case, the methodology may further comprise implanting a third transistor region associated with a third transistor device in the semiconductor device using a third implantation process to adjust a threshold voltage associated with the third transistor device, and implanting a portion of a fourth transistor region associated with a fourth transistor to form a source/drain region associated with the fourth transistor using the third implantation process. The source/drain regions of the third transistor may then be formed using a fourth implantation process, such as an LDD implant optimized for low voltage MOSFET devices.
Another aspect of the present invention involves a method of forming a source/drain region in a semiconductor device, comprising selectively implanting a first transistor region to adjust a threshold voltage associated with a first transistor device and a portion of a second transistor region to form a source/drain region associated with a second transistor device using a single implantation process. The invention further comprises methods for fabricating MOSFET transistors in a semiconductor device, comprising adjusting a threshold voltage of a first transistor device using a first threshold adjust implantation process, and forming a source/drain region of a second transistor device using the first threshold adjust implantation process.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.